Multi-layer printed circuit cards are commonplace in the electronics industry. A very important aspect of these circuit cards is the construction of vias, or through-holes, which make contact to one or more of the wiring layers while not making contact to any other layer. These vias connect one layer of the card to another layer, and make possible complex 3 dimensional interconnections.
Typically in such a multi-layer card all wiring layers are patterned first either singly or as both sides of a conductor-dielectric-conductor sandwich (a `core`); the layers stacked up,and isolated from each other by dielectric layers (a `fill`), and laminated under heat and pressure into a single card; and finally the through holes drilled and then made conducting by seeding of the walls of the drilled holes and electroplating. Often the outer layers of the card are plated at this time also, so that the conductor thickness of the outer layers is equal to or greater than the thickness of the copper `barrel` that lines the sides of the drilled hole.
The process of not making contact to an internal or external wiring layer, or layer of selectively patterned electrical conductors, is relatively easy since all that is required is there be no conductor in the area of the board through which the via is to be made. However, many of the layers of a multi-layer circuit card may be almost continuous conductor, with patterned holes in the conductive layer only to avoid contact with vias. These layers are termed reference layers, and carry the constant potential voltages (for example, ground, +5 Volts, etc) that power electronics connected to these circuit cards. It is these patterned holes in reference layers, called either clearance holes or anti-pads in the industry, that is the subject of this invention.
In a densely wired circuit card it is possible to have so many holes in a reference layer in a region of circuit card that there is almost no metal left to conduct currents. For example, in a complex, high resolution circuit card it is not unusual for holes to be drilled on a 0.050 inch grid, with clearance holes of diameter 0.044" in the reference layers. On an adjacent layer, directly above or below this reference layer, there can be as many as 3 circuit lines, each 0.004 inch wide and separated by 0.004 inch, between two such vias. Thus the 0.006" conductor must serve as the reference return of a transmission line for the 3 signals. If the signals are very fast and especially if there is misalignment between the reference layer and the wiring layer, the lack of a substantial reference layer can cause the signals to couple to each other, or `cross-talk`. Similarly if the clearance holes in reference layers are too large there may not be enough copper to carry the substantial currents consumed by the devices attached to the cards. Similarly if the clearance holes in the reference layers are too large they will not serve to isolate signal wiring on a layer above the reference layer from signal wiring in a layer below, and the two signal layers can couple or `crosstalk`. Any of these conditions can cause electrical failure.
Smaller clearance holes would solve the problem, but smaller holes cannot be easily constructed due to misalignment between wiring layers, drill wander during drilling, pressure induced motion of region of the circuit card during the process of laminating the layers together, etc. Were smaller clearance holes to be made, the aforementioned errors could cause the drilled hole to contact the reference plane, causing an unwanted connection or `short` after electroplating of the vias.
A further difficulty in multi-layer circuit card construction is the inability to make circuit cards with different metal thicknesses on different layers. While it is possible to do this to a limited degree, what is generally required is to selectively etch different layers for different times, which is difficult to impossible if the two layers are part of a `core`.
It is an object of the present invention to provide a printed circuit board (PCB) and a process for making the printed circuit boards with either solid filled and redrilled or electrocoated reference planes.
It is another object of the present invention to provide a process for making printed circuit boards where the holes are filled by a lamination process as follows: Fill material is coated on a carrier film or foil, and dried.
It is another object of the present invention to provide a process and PCB wherein a board and a mask film or foil are both drilled with the pattern of the holes to be plated through and filled.
It is another object of the present invention wherein the holes are deburred, and chemically cleaned.
It is another object of the present invention to provide a process and PCB wherein holes are activated and electrolessly and/or electrolyticly plated, along with both surfaces of the board.
It is another object of the present invention to provide a process and PCB wherein the drilled mask is aligned over the plated through holes in the board and a sheet coated with the fill material is placed over the mask.
It is another object of the present invention to provide a process and PCB wherein the board, mask and fill sheet are placed in a laminating press and vacuum laminated with heat and pressure to force the fill material into the plated through holes, and then to cure the fill material, after which the press is cooled and pressure released.
It is another object of the present invention to provide a process and PCB wherein the board is removed from the press and the mask and fill carrier sheets are peeled from the board.
It is another object of the present invention to provide a process and PCB wherein the fill material nubs, and any filled material which bled between the board and mask, are removed by mechanical abrasion, and/or chemical processes.
It is another object of the present invention to provide a PCB and a processes of circuit card construction with internal reference layers whereby the internal reference layers can have thickness substantially different from the thickness of adjacent signal wiring layers, and where the clearance holes in the reference layer are substantially aligned to the drilled holes.